1. Field of the Invention
The present invention relates generally to amplifiers for use within integrated circuits, and more particularly, to an amplifier capable of amplifying an input signal, and generating a corresponding output signal, that vary between an extended operating voltage range.
2. Description of the Related Art
CMOS is a widely used technology for integrated circuits, particularly because CMOS transistors can be fabricated using relatively small amounts of semiconductor chip area, and because they minimize power consumption. The electrical properties of CMOS technology are well understood. The voltage that can be used to power CMOS circuits is dependent upon the physical dimensions of the individual transistors (i.e., their geometry) and the particular processing utilized in the manufacturing of the transistors.
Many CMOS integrated circuits can be operated at power supply ranges of 5 volts or less. Processing techniques have been developed and are known to those skilled in the art for producing highly-dense CMOS integrated circuits which operate over a power supply range of 5 volts or less. These integrated circuits produce output signals which also range approximately between ground and +5 volts or less, respectively. It will be understood that mention of +5 volts is merely exemplary, and that CMOS integrated circuits can operate at power supply voltages other than 5 volts. However, the device geometries used to form CMOS transistors must be selected to reliably withstand the power supply operating range in use. Generally speaking, the larger the operating voltage range, the larger device geometries must be used.
In some instances, a CMOS integrated circuit must drive or control some other device which requires an input signal having a voltage magnitude greater than 5 volts (i.e., greater than the power supply operating range for which such CMOS transistors are designed). One example is the need to drive liquid crystal display (LCD) screens of the type used in hand-held games, hand-held computers, laptop/notebook computers, and more recently thin-screen desktop displays. LCD displays used in computer screens require a large number of input control signals which must operate at voltages from 8 volts to as high as 20 volts. In order for a CMOS integrated circuit to generate an output signal having such an increased voltage magnitude, then the power supply range for such CMOS integrated circuit must also have an increased voltage magnitude.
In general, the higher the power supply voltage needed, the larger the individual transistors must be to withstand such increased voltages and to meet reliability standards; in addition, the use of larger power supply voltages necessitates special processing considerations. Larger device geometries and more complex processing generally result in higher manufacturing costs for a particular integrated circuit, since the total area of the integrated circuit, and the complexity of the manufacturing process, are both major factors in determining the cost of a particular circuit.
There are several mechanisms which limit the voltage that a particular CMOS transistor can tolerate. Among the failure mechanisms that can plague such CMOS devices are: a) channel breakdown due to excessive voltage appearing between the source and drain terminals of the CMOS transistor; b) dielectric breakdown of the gate oxide, which is a destructive mechanism; and c) junction breakdown corresponding to the reverse voltage breakdown of the diode which appears at the source and drain of all CMOS transistors.
One circuit technique for allowing CMOS logic integrated circuits to tolerate higher voltages without degradation is described in U.S. Pat. No. 5,465,054, issued to Erhart, and assigned to the assignee of the present invention. In the ""054 patent, so-called xe2x80x9csuper-transistorsxe2x80x9d are used to allow a full-range input signal to drive CMOS transistors made using a low-voltage CMOS process. Each super-transistor includes a CMOS input shielding transistor and a CMOS switching transistor. Each input shielding transistor has its gate terminal coupled to a shielding voltage set approximately midway between ground potential and the full-range VDD power supply voltage. The shielding transistor is coupled between the full-range input signal and the gate of the switching transistor. The drain of each switching transistor is, in turn, coupled by an output shielding transistor to a full-range output terminal for providing a full-range output signal. The gate terminals of each output shielding transistor are also coupled to the shielding voltage. The input shielding transistors and output shielding transistors prevent any gate oxide voltage or channel voltage from exceeding one-half of the voltage difference between ground potential and the positive power supply voltage VDD, while allowing the output signal to swing full range from ground potential to VDD.
The aforementioned U.S. Pat. No. 5,465,054 discloses various logic gates (inverters, NAND gates, transmission gates). However, CMOS integrated circuits must often include amplifiers for processing analog signals, as well. Such amplifiers may be constructed using larger-geometry devices to reliably tolerate increased power supply voltages, but the use of such larger-geometry devices again increases chip area, particularly when such an amplifier must be repeated tens, or hundreds, of times on a single integrated circuit.
In view of the foregoing, it is an object of the present invention to provide a CMOS amplifier circuit adapted to be fabricated within an integrated circuit using relatively small device geometries, and CMOS processing techniques, normally associated with a low voltage (e.g., 5 volt) power supply range, but which is capable of operating over an extended power supply range to amplify input signals that exceed the typical low voltage range.
It is another object of the present invention to provide such a CMOS amplifier circuit which permits the use of larger power supply voltages for generating output signals of greater voltage magnitude while retaining high density advantages of low-voltage CMOS processing.
It is still another object of the present invention to provide such a CMOS amplifier circuit which uses low-voltage type CMOS transistors in conjunction with higher-voltage power supply ranges while preventing channel breakdown, gate oxide breakdown, and junction breakdown failure modes.
A further object of the present invention is to provide such a CMOS amplifier circuit which uses low-voltage type CMOS transistors in conjunction with higher-voltage power supply ranges without impairing the reliability of such integrated circuits.
A still further object of the present invention is to provide such a CMOS amplifier circuit which uses low-voltage type CMOS transistors in conjunction with higher-voltage power supply ranges without significantly increasing the cost of manufacturing such integrated circuits.
Yet another object of the present invention is to provide such an extended range amplifier that includes differential inputs.
These and other objects of the present invention will become more apparent to those skilled in the art as the description of the present invention proceeds.
Briefly described, and in accordance with preferred embodiments thereof, the present invention relates to a differential circuit formed between a pair of power supply conductors that define an operating voltage range; the differential circuit includes a negative input terminal and a positive input terminal for receiving first and second voltages, respectively, each ranging within the aforementioned operating voltage range. The differential circuit includes first and second CMOS transistors coupled with each other to form a differential pair; drain terminals of the first and second CMOS transistors are coupled to a source of reference current, while the gate terminals of the first and second CMOS transistors are coupled to the negative input terminal and positive input terminal, respectively, for dividing the reference current between source terminals of the first and second CMOS transistors in accordance with differences between the first and second voltages.
The differential circuit also includes first and second level shift circuits coupled to the negative input terminal and positive input terminal, respectively, for receiving the first and second voltages, and for producing first and second level-shifted voltages; the first level-shifted voltage is of a lower voltage than the first voltage and is, at least partially, responsive to changes in the first voltage. The second level-shifted voltage bears a similar relationship with the second voltage. Preferably, such level-shifted voltages range between the voltage of one of the power supply conductors and a voltage that lies approximately midway between the first and second power supply voltages.
The source terminals of the first and second CMOS transistors are coupled to drain terminals of third and fourth CMOS transistors, respectively. The gate terminal of the third CMOS transistor is coupled to the first level shift circuit for receiving first level-shifted voltage, and the gate terminal of the fourth CMOS transistor is coupled to the second level shift circuit for receiving the second level-shifted voltage. The source terminals of the third and fourth CMOS transistors provide first and second complementary components of the reference current.
In one aspect of the present invention, the differential circuit further includes fifth and sixth CMOS transistors, the source terminals of which are coupled, respectively, to the drain terminals of the first and second CMOS transistors. The gate terminals of the fifth and sixth CMOS transistors are coupled, respectively, to the first and second level shift circuits for receiving, respectively, the first level-shifted voltage and the second level-shifted voltage. The drain terminals of the fifth and sixth CMOS transistors are coupled in common to the source of reference current, preferably through a seventh CMOS transistor; in this case, the seventh CMOS transistor includes a source terminal coupled with the common drain terminals of the fifth and sixth CMOS transistors; the gate terminal of the seventh CMOS transistor is coupled to a shield voltage, and the drain terminal of the seventh CMOS transistor is coupled to the source of reference current. Preferably, the shield voltage that is coupled to the gate terminal of the seventh CMOS transistor is a voltage approximately midway within the operating voltage range defined by the first and second power supply conductors.
In the preferred embodiment of such differential circuit, the first and second CMOS transistors are n-channel devices, while the third, fourth, fifth, sixth, and seventh CMOS transistors are p-channel devices. The first, second, third, fourth, fifth, and sixth CMOS transistors are all characterized by gate-to-source breakdown voltages, and a gate-to-drain breakdown voltages, of less than the operating voltage range defined by the first and second power supply voltages. Thus, such devices are normally designed to operate with a smaller operating voltage and are physically smaller than devices designed to operate at larger operating voltages. However, the above-described differential circuit prevents excessive voltages from developing across the terminals of such CMOS transistors even though the operating voltage range of the differential circuit is extended.
In another aspect of the present invention, the differential circuit is part of a differential amplifier that includes a current steering circuit, a current mirror circuit, and an output port. The current steering circuit has first and second input terminals coupled, as by way of example, via the aforementioned third and fourth CMOS transistors, to the source terminals of the first and second CMOS transistors for receiving the currents conducted thereby. The current steering circuit also includes first and second output terminals for conducting output currents determined in accordance with currents received by the first and second input terminals. The current mirror circuit has an input terminal coupled with the first output terminal of the current steering circuit for conducting the output current supplied thereby; the current mirror circuit also includes an output terminal for conducting a corresponding mirrored current. The output port is coupled to the output terminal of the current mirror circuit and to the second output terminal of the current steering circuit for providing an output voltage within the operating voltage range.